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来源：百度文库 编辑：杭州交通信息网 时间：2024/04/29 14:05:54
Fractional-N Synthesis
In fractional-N synthesis, counters are used to provide a variable modulus, or counters are used to provide for .pulse swallowing.. If you have a counter that can divide by 10 and divide by 11, then you can make a circuit where the counter divides by one factor for some number of clock cycles and then divides by the other number for perhaps a different number of clocks. The resultant frequency is then the ratio of how many clocks were divided by 10 to how many were
divided by 11. This technique requires a variable modulo counter,another counter for the selection, and logic for state control
One disadvantage of this technique is that the jitter is increased due to the difference in the modulo, with the output frequency being 10 times less, then abruptly 11 times less, and so on, in a fine time scale. The advantage is that it is considered a simpler structure (but only from the old point of view using discrete, small scale integrated circuits).
The other commonly used method of fractional-N synthesis is to drop an output clock pulse based on some rule derived from a counter state machine. For example, if you drop every 4th clock out of every 5 input clocks, the output rate is 4/5 the input rate. This is known as .pulse swallowing.. This also results in a large amount of jitter due to the missing clock
period.
In fractional-N synthesis, counters are used to provide a variable modulus, or counters are used to provide for .pulse swallowing.. If you have a counter that can divide by 10 and divide by 11, then you can make a circuit where the counter divides by one factor for some number of clock cycles and then divides by the other number for perhaps a different number of clocks. The resultant frequency is then the ratio of how many clocks were divided by 10 to how many were
divided by 11. This technique requires a variable modulo counter,another counter for the selection, and logic for state control
One disadvantage of this technique is that the jitter is increased due to the difference in the modulo, with the output frequency being 10 times less, then abruptly 11 times less, and so on, in a fine time scale. The advantage is that it is considered a simpler structure (but only from the old point of view using discrete, small scale integrated circuits).
The other commonly used method of fractional-N synthesis is to drop an output clock pulse based on some rule derived from a counter state machine. For example, if you drop every 4th clock out of every 5 input clocks, the output rate is 4/5 the input rate. This is known as .pulse swallowing.. This also results in a large amount of jitter due to the missing clock
period.
频率-N 综合
在频率-N 综合中，柜台用来提供一个可变的率, 或柜台用来提供。跳动忍受。。如果你有在 10 点之前能分开和在 11 点之前分歧的一个柜台,那么你能作一个柜台分歧一个因素对于时钟的一些数字循环然后为也许一个时钟的不同数字藉着另一个数字分开的线路。 合量频率是然后时钟在 10 点之前被分开到多少是多少的比
在 11 点之前分开了。 这技术以柜台为模需要一个变数,另外的一个柜台为选择 , 和逻辑对于州控制
这技术的缺点是由于不同跳动被增加在那以,为模随着作为 10 次比较少量的输出频率, 然后突然地 11 次比较少量, 等等, 在一个好的时间表中。 利益是它被视为较简单的结构。 (但是只有从使用的旧的观点不连续的, 小规模整合了线路)
微少-N 综合的普遍二手方法将降低以起源于一部柜台州机器的一些规则为基础的输出时钟脉膊的另一个。 举例来说，如果你从每一 5个输入时钟降低每个第 4个时钟,输出率是 4/5 输入率。 这即是。跳动忍受。。 由于不见的时钟这也造成很多的跳动
时期。